1. Field of the Invention
This invention relates to the field of electronic circuit design for programmable logic devices and, more particularly, to increasing the reliability and/or quality of such circuit designs.
2. Description of the Related Art
A programmable logic device (PLD) is a type of integrated circuit that can be programmed to perform specified logic functions. A field programmable gate array (FPGA) is one variety of PLD which can include several different types of components. An FPGA usually includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and a programmable interconnect structure which links the CLBs and IOBs. Some FPGAs also can include specialized components such as delay-locked loops, RAMs, processors, and the like.
Modern PLDs not only are large in size, but also are complex in nature. Such devices must be rigorously tested as a malfunction can produce unexpected results. After the PLD is fabricated, it can be tested through known testing methods. Commonly, testing involves the creation of a number of different test patterns targeted at exercising various portions or resources of the PLD. A test pattern refers to a configuration bitstream and a corresponding set of input vectors. The test patterns typically are designed by a team of test engineers. When loaded into the PLD under test, the configuration bitstream configures the PLD with a test design. Once configured with a test design, the input vectors can be applied to the PLD. Actual outputs from the PLD can be compared with expected outputs to identify fault conditions within the PLD.
To test routing resources within an FPGA, for example, a plurality of test designs are sequentially loaded and tested. The test designs typically are based upon a full FPGA design which supports “walking one” or “walking zero” chain methodologies. “Walking” one or zero refers to the process of initializing the entire chain or signal path through the device to logic one or zero respectively. Each segment of the chain separated by a flip-flop or other similar storage element requires one clock cycle to transfer data. Once the chain is initialized to logic zero or one, the opposite value is introduced and walked through the signal path. For instance, if initialized to logic zero, a logic one is introduced and walked through the signal path. This process takes M clock cycles where M is the number of storage elements in the signal path through which the value must pass. The opposite value shows up at the output of the design after M clock cycles in a successful test.
Each test pattern can be designed to test for one or more different fault models. For example, a test pattern can be designed to test or detect a particular type of fault such as a stuck at 0 (SA0) or a stuck at 1 (SA1) fault in reference to a signal being stuck in a low or high state. Each test pattern further can be targeted at testing specific routing resources of the PLD under test. Detection of an SA0 or SA1 fault when executing a particular test pattern can provide an indication as to which element of the PLD is malfunctioning. Test patterns can be designed to test other varieties of faults beyond SA0 or SA1 faults.
Modern PLDs, however, include a very large number of routing resources. To test each routing resource of a PLD would be impractical due to the significant time and cost involved. Also, in some cases, it is not possible to isolate and test a routing resource by itself because that resource can only be accessed through some other routing resource. Notwithstanding, it is desirable for PLD manufacturers to test as many routing resources as possible. Accordingly, a significant number of test patterns are run using a stochastic approach. Due to overlap with respect to the test patterns, some routing resources are tested or exercised more frequently than others. Other routing resources, however, may not be tested at all.
After meeting necessary quality standards, the PLD is made available to end users, in this case design engineers, responsible for designing a circuit that is to be implemented using the PLD. At some point, the circuit design is routed. Conventional software-based design tools take several factors into account when routing a circuit design. These factors can include signal propagation delays and power consumption. The circuit design can be routed in such as way as to minimize signal propagation delays and/or power consumption.
While conventional design tools consider different factors when routing a circuit design, the reliability of the routing resources selected for a route is not among those factors. In illustration, when given a choice between two routing resources, a router is equally likely to select a routing resource that has been thoroughly tested as one that has not. Such is the case, as timing constraints and, possibly, power consumption largely drive the routing process. It would be beneficial to determine measures of reliability for routing resources of a PLD. Further, it would be beneficial to route the PLD such that routing resources considered to be more reliable are favored over routing resources which are considered less reliable.